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AD9985A
Table 38. Detected Coast Input Polarity Status
16
4
Analog Input Bandwidth
Polarity Status
0
1
Result
Coast polarity negative
Coast polarity positive
This bit controls the bandwidth of the red, green,
and blue analog inputs. In most applications, the
analog input bandwidth should be set to its maximum
This indicates that Bit 1 of Register 5 is the 4:2:2
output mode select bit.
(300 MHz). When there is excessive noise on the
analog inputs, reducing the bandwidth can help
15
1
4:2:2 Output Mode Select
suppress the noise.
A bit that configures the output data in 4:2:2 mode.
Table 43. Anti-Aliasing Filter
This mode can be used to reduce the number of data
lines used from 24 down to 16 for applications using
YUV, YCbCr, or YPbPr graphics signals. A timing
Select
0
1
Input Bandwidth
300 MHz
7 MHz
diagram for this mode is shown in Figure 11.
19
7:0
Red Target Code
Recommended input and output configurations are
shown in Table 39 and Table 40.
Table 39. 4:2:2 Output Mode Select
This specifies the targeted value of the final offset
for the red channel when auto-offset is used
(Register 0x1D, Bit 7 = 1). Default is 4.
Select
Output Mode
1A
7:0
Green Target Code
0
1
4:2:2
4:4:4
This specifies the targeted value of the final offset
for the green channel when auto-offset is used
Table 40. 4:2:2 Input/Output Configuration
(Register 0x1D Bit 7 = 1). Default is 4.
Channel
Red
Input Connection
V
Output Format
U/V
1B
7:0
Blue Target Code
Green
Blue
16
7
Y
U
Extra PLL Divider
Y
High impedance
This specifies the targeted value of the final offset
for the blue channel when auto-offset is used
(Register 0x1D, Bit 7 = 1). Default is 4.
A bit that can add an additional divide-by-2 into the
1D
7
Auto-Offset Enable
PLL divide ratio. Enabling this function at pixel
frequencies below 20 MHz can result in improved PLL
Enables the auto-offset circuitry. Default is 0.
jitter performance, as it allows the VCO to run at a
higher frequency, resulting in lower jitter.
1D
6
Hold Auto-Offset
Table 41. PLL VCO Divide
Select PLL Divider
Holds the offset output of the auto-offset at the
current value. Default is 0.
0
Off
1D
1:0
Update Mode
1
Extra divide-by-2
16
6-5
SOGIN Bandwidth
Changes the update rate of the auto-offset.
Default is 10.
Two bits that can control the bandwidth of the sync-
on-green input (SOGIN). In most applications, the
SOGIN bandwidth should be set to its maximum
Table 44. Auto-Offset Update Rate
Update Mode Auto-Offset Update Timing
(300 MHz). When there is excessive noise on SOGIN,
reducing the bandwidth can help suppress the noise.
Table 42. SOGIN Bandwidth
Select
Pulses Filtered
00
300 MHz
01 or 10
13 MHz
11
6.5 MHz
00
01
10
Every clamp cycle
Every 16 clamp cycles
Every 64 camp cycles
Rev. 0 | Page 25 of 32
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